We suffer from 'process anxiety', but are smaller chips really better?

According to IC Insights, a well-known chip research firm, it will take at least five years and 1 trillion yuan to catch up with the world's largest foundry, TSMC.

In 2020, TSMC achieved a net profit after tax of 517.885 billion yuan with advanced processing capabilities on chips. anti vibration table Technically, this is key to the operation of consumer electronics like phones, tablets, and computers.

The top five wafer foundries in the world - TSMC, Samsung, UMC, Grofonde - only kept up with SMIC's process, while UMC and Grofonde, ranking third and fourth, almost gave up advanced processes.

The UMC gave up 12 nm process research and development in 2018, and Grofonde, semiconductor test the second largest electronic chip foundry in the world, announced in January that it would stop developing 7 nm FinFETs. As far as the global foundry and IDM model (Integrated Device Manufacturing) is concerned, only TSMC, Samsung, and Intel (7 nm taped in) are capable of manufacturing 7 nm and smaller wafers.

There are many ways to improve the performance of smaller chips. Why did major chipmakers abandon advanced process research and development?

Chip evolution

The chip's advanced process aims to decrease its size, specifically the gate width of the transistor. A smaller number results in higher transistor density, lower power consumption, and improved performance. However, achieving this is no easy feat. voltage probe The development of chips typically adheres to Moore's Law, with performance doubling every 18 months to two years. This allows for a greater number of transistors to be installed on a chip, ultimately enhancing its overall performance.

A transistor's size was reduced to nanometers in 2004, in the 1980s. At this time, the problem continues to emerge, the integration and fineness of nanoscale transistors are very high, you know that 0.1 nm on an atom, the limit of human physical cognition can be imagined.

Quantum tunneling and short channel effects are the two most representative problems. When the conductive channel length of a metal oxide semiconductor field effect transistor is reduced to ten nm or even several nm, the short channel effect occurs. It includes "threshold voltage reduction with decreasing channel length, drain barrier reduction, carrier surface scattering, velocity saturation, ionization, and hot electron effects".

In fact, because the transistor is a tube with three ports - electrons run from the source end to the drain end, so that information transmission can be completed, and the rhythm of the "run" is the gate end. The voltage change corresponding to the port determines the switch.

Nanoscale wafers with short channels

The chip's efficiency is determined by the length of the channel based on the fact that most of the time the electronic speed is running at full speed. The size of a short pipe decreases, and the electric field interference that can be ignored when it is long becomes more and more, resulting in an inability to close the gate end tightly, which is called the short channel effect.

The short channel effect on nanochips is that since the channel tube is not charged, as long as there is a power supply, the transistors on the chip will continue to leak electricity, resulting in heat and power consumption on the chip seriously affecting its service life.

It was believed that the fin-type field-effect transistor (FinFET) strengthened the ability of the gate to control the channel, reduced the short channel effect, and delayed the occurrence of problems before Professor Hu Zhengming invented it in 1999. To achieve 5 nm, TSMC and Samsung use this technology now.

Yet, as the technology advances to 3 nm, the three-sided gate control system of FinFET begins to weaken, allowing the short-channel effect to resurface. This issue was only resolved with the emergence of a new transistor structure in the following generation known as Gate-all-around surround Gate technology (GAA structure). Essentially, this involves wrapping the channel with a four-sided gate, resulting in lower operating voltage, reduced leakage, decreased overall chip power consumption and operating temperature, and prolonging Moore's Law. Both Samsung's 3 nm and TSMC's 2 nm developments utilize this technique.